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Influence of line-edge roughness on multiple-gate tunnel field-effect transistors
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Influence of line-edge roughness on multiple-gate tunnel field-effect transistors
- 資料種別
- 記事
- 著者
- Woo Young Choi
- 出版者
- IOP Publishing
- 出版年
- 2017-02-27
- 資料形態
- デジタル
- 掲載誌名
- Japanese Journal of Applied Physics 56 4S
- 掲載ページ
- p.04CD06-
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デジタル
- 資料種別
- 記事
- 著者標目
- 出版年月日等
- 2017-02-27
- 出版年(W3CDTF)
- 2017-02-27
- タイトル(掲載誌)
- Japanese Journal of Applied Physics
- 巻号年月日等(掲載誌)
- 56 4S
- 掲載巻
- 56
- 掲載号
- 4S
- 掲載ページ
- 04CD06-
- 掲載年月日(W3CDTF)
- 2017-02-27
- ISSN(掲載誌)
- 00214922
- 出版事項(掲載誌)
- IOP Publishing
- 対象利用者
- 一般
- DOI
- 10.7567/jjap.56.04cd06
- 作成日(W3CDTF)
- 2017-02-27
- 著作権情報
- http://iopscience.iop.org/info/page/text-and-data-mininghttp://iopscience.iop.org/page/copyright
- 関連情報(URI)
- 参照
- Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET logic circuitsStochastic Variability in Silicon Double-Gate Lateral Tunnel Field-Effect TransistorsDemonstration of L-Shaped Tunnel Field-Effect TransistorsDouble-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slopeGreen Transistor - A V<inf>DD</inf> Scaling Path for Future Low Power ICsComparative Study of Tunneling Field-Effect Transistors and Metal–Oxide–Semiconductor Field-Effect TransistorsBandgap engineering of group IV materials for complementary n and p tunneling field effect transistorsImpact of LER and Random Dopant Fluctuations on FinFET Matching PerformanceThe Tunnel Source (PNPN) n-MOSFET: A Novel High Performance TransistorTunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/decDesign of U-Shape Channel Tunnel FETs With SiGe Source RegionsImpact of Line-Edge Roughness on FinFET Matching PerformanceTunnel FET technology: A reliability perspectiveComplementary tunneling transistor for low power applicationGate Line Edge Roughness Model for Estimation of FinFET Performance VariabilityTunneling and Occupancy Probabilities: How Do They Affect Tunnel-FET Behavior?Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operationLow-subthreshold-swing tunnel transistorsNovel Bipolar-Enhanced Tunneling FET With Simulated High On-CurrentTunnel Field-Effect Transistor With an L-Shaped GateInAs/Si Hetero-Junction Nanotube Tunnel TransistorsStudy of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETsStudy of Random Dopant Fluctuation Induced Variability in the Raised-Ge-Source TFETIntrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughnessStatistical variability and reliability in nanoscale FinFETsTunnel field-effect transistor without gate-drain overlapMixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application DomainScaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction EngineeringInvestigation of tunnel field-effect transistors as a capacitor-less memory cell
- 連携機関・データベース
- 国立情報学研究所 : CiNii Research
- 提供元機関・データベース
- CrossrefCiNii Articles
- NII論文ID
- 210000147566