Instruction Issuing Mechanism for VLIW Processors

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Instruction Issuing Mechanism for VLIW Processors

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Provided by：国立国会図書館デジタルコレクション

Contents
p1
1 Introduction
p10
1.1 Background and Objectives
p10
1.2 Organization of the Thesis
p14
2 Scheduling Strategy for Integrated Instruction-Level Parallelism of Scalar and Vector Operations
p15

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Material Type: 博士論文
Title: Instruction Issuing Mechanism for VLIW Processors
Author/Editor: 仲池卓也 [著]
Author Heading: 仲池, 卓也ナカイケ, タクヤ
Publication, Distribution, etc.: [仲池卓也]
Publication Date: 2000
Publication Date (W3CDTF): 2000
Extent: 1冊
Alternative Title: VLIW計算機のための命令供給機構に関する研究 VLIW ケイサンキノタメノメイレイキョウキュウキコウニカンスルケンキュウ
Degree grantor/type: 東北大学
Date Granted: 平成12年3月23日
Date Granted (W3CDTF): 2000
Dissertation Number: 甲第7546号
Degree Type: 博士 (情報科学)
Note (Dissertation): 博士論文
Place of Publication (Country Code): JP
Text Language Code: eng
NDLC: UT51
Note (General): 博士論文
Holding library: 国立国会図書館
Call No.: UT51-2000-S751
Data Provider (Database): 国立国会図書館 : 国立国会図書館蔵書
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 000000394246
http://id.ndl.go.jp/bib/000000394246
Bibliographic Record Category (NDL): 213