Planarization process for fabricating multi-layer Nb integrated circuits incorporating top active layer

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Material Type: 記事
Title: Planarization process for fabricating multi-layer Nb integrated circuits incorporating top active layer
Author Heading: SATOH T.
Publication Date: 2009
Publication Date (W3CDTF): 2009
Periodical title: IEEE Trans. Appl. Supercond.
No. or year of volume/issue: 19 3
Volume: 19
Issue: 3
Pages: 167-170
Publication date of volume/issue (W3CDTF): 2009
Target Audience: 一般
Data Provider (Database): 国立情報学研究所 : CiNii Research
https://cir.nii.ac.jp/
Original Data Provider (Database): CiNii Articles
NAID: 10026825074