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PIPELINED IC ARCHITECTURE FOR RADON TRANSFORM COMPUTATIONS IN A MULTIPROCESSOR ARRAY (UCRL ; UCRL-CR-104184)

PIPELINED IC ARCHITECTURE FOR RADON TRANSFORM COMPUTATIONS IN A MULTIPROCESSOR ARRAY (UCRL ; UCRL-CR-104184)
Paper図書
AGI, I.// HURST, P.J.// CURRENT, K.W. (LAWRENCE LIVERMORE NATIONAL LAB., CA (USA)// CALIFORNIA UNIV., DAVIS, CA (USA). DEPT. OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE)University of California Research Laboratory(University of California Research Laboratory)1990.
Other Libraries in Japan
  • Author HeadingAGI, I. HURST, P.J. CURRENT, K.W. CALIFORNIA UNIV., DAVIS, CA

EVALUATION AND IMPLEMENTATION OF TESTABILITY SCHEMES FOR GATE ARRAY INTEGRATED CIRCUIT DESIGN. (UCRL ; UCRL-15676)

EVALUATION AND IMPLEMENTATION OF TESTABILITY SCHEMES FOR GATE ARRAY INTEGRATED CIRCUIT DESIGN. (UCRL ; UCRL-15676)
Paper図書
CURRENT, K.W.(et al.)California Univ., Livermore (USA). Lawrence Livermore Lab(California Univ., Livermore (USA). Lawrence Livermore Lab)1985.
Other Libraries in Japan
  • Author HeadingCURRENT, K.W.

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