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A unified approach for timing verification and delay fault testing

A unified approach for timing verification and delay fault testing
Paper図書
Mukund Sivaraman and Andrzej J. StrojwasKluwer Academicc1998
Other Libraries in Japan
  • Author HeadingSivaraman, Mukund Strojwas, Andrzej J.

VLSI design for manufacturing : yield enhancement

VLSI design for manufacturing : yield enhancement
Paper図書
by Stephen W. Director, Wojciech Maly, Andrzej J. StrojwasKluwer Academic Publishersc1990
Other Libraries in Japan
  • Author HeadingMaly, W. Strojwas, Andrzej J. Director, Stephen W.

Selected papers on statistical design of integrated circuits

Selected papers on statistical design of integrated circuits
Paper図書
edited by Andrzej J. StrojwasIEEE Pressc1987
Other Libraries in Japan
  • Author HeadingStrojwas, Andrzej J.

Yield modelling and defect tolerance in VLSI : papers presented at the International Workshop on Designing for Yield, Oxford, 1-3 July 1987

Yield modelling and defect tolerance in VLSI : papers presented at the International Workshop on Designing for Yield, Oxford, 1-3 July 1987
Paper図書
edited by Will Moore, Wojciech Maly, and Andrzej StrojwasA. Hilgerc1988
Other Libraries in Japan
  • Author HeadingMoore, Will Maly, W. Strojwas, Andrzej J.

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