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Energy-efficient V<sub>aq</sub>-based switching scheme with bottom-plate sampling for SAR ADCs
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Energy-efficient V<sub>aq</sub>-based switching scheme with bottom-plate sampling for SAR ADCs
- 資料種別
- 記事
- 著者
- Huang Conggui
- 出版者
- The Institute of Electronics, Information and Communication Engineers
- 出版年
- 2025-04-10
- 資料形態
- デジタル
- 掲載誌名
- IEICE Electronics Express 22 7
- 掲載ページ
- p.20250046-20250046
資料詳細
要約等：
- <p>A novel digital-to-analog converter (DAC) switching scheme has been developed to improve the power efficiency of successive approximation register ...
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デジタル
- 資料種別
- 記事
- 著者標目
- 出版年月日等
- 2025-04-10
- 出版年（W3CDTF）
- 2025-04-10
- タイトル（掲載誌）
- IEICE Electronics Express
- 巻号年月日等（掲載誌）
- 22 7
- 掲載巻
- 22
- 掲載号
- 7
- 掲載ページ
- 20250046-20250046
- 掲載年月日（W3CDTF）
- 2025-04-10
- ISSN-L（掲載誌）
- 13492543
- 出版事項（掲載誌）
- The Institute of Electronics, Information and Communication Engineers
- 本文の言語コード
- en
- 対象利用者
- 一般
- DOI
- 10.1587/elex.22.20250046
- 参照
- An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative comparatorA highly energy-efficient, area-efficient switching scheme for SAR ADC in biomedical applicationsA Low-Energy and Area-Efficient Vaq-Based Switching Scheme with Capacitor-Splitting Structure for SAR ADCsA 10-Bit 120 kS/s SAR ADC Without Reset Energy for Biomedical ElectronicsA Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor ApplicationsA 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DACArea-Efficient Capacitor-Splitting Switching Scheme with a Nearly Constant Common-Mode Voltage for SAR ADCsLow-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA TechniqueA 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ProcedureLow-energy and area-efficient tri-level switching scheme for SAR ADCHigh energy-efficient switching scheme for SAR ADC with low common-mode level variation<i>V</i> <sub>aq</sub> ‐based tri‐level switching scheme for SAR ADCLow-energy and area-efficient switching scheme for SAR A/D converterHigh Energy Efficiency and Linearity Switching Scheme Without Reset Energy for SAR ADCVaq-Assisted Low-Power Capacitor-Splitting Switching Scheme for SAR ADCsA Four-Level Switching Scheme for SAR ADCs with 87.5% Area Saving and 97.85% Energy-ReductionLow‐power successive approximation ADC using split‐monotonic capacitive DACComparator common-mode variation effects analysis and its application in SAR ADCsAn energy‐efficient switching scheme based on distributing most significant bit capacitors for successive approximation register analog‐to‐digital converter500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DACV <sub>CM</sub> ‐based monotonic capacitor switching scheme for SAR ADCEnergy‐efficient hybrid capacitor switching scheme for SAR ADCSAR ADC architecture with 98% reduction in switching energy over conventional schemeA 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-$\mu$m CMOS for Medical Implant DevicesAn Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCsA 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient SwitchingUltra-low energy switching scheme for SAR ADCSwitch-back based on charge equalization switching technique for SAR ADCCentral span switching structure for SAR ADC with improved linearity and reduced DAC powerEnergy and area-efficient tri-level switching procedure based on half of the reference voltage for SAR ADCVariable resolution SAR ADC architecture with 99.6% reduction in switching energy over conventional schemeTri-level capacitor-splitting switching scheme with high energy-efficiency for SAR ADCs
- 連携機関・データベース
- 国立情報学研究所 : CiNii Research
- 提供元機関・データベース
- Japan Link CenterCrossref