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- 資料種別
- 記事
- 著者標目
- 出版年月日等
- 2010
- 出版年（W3CDTF）
- 2010
- タイトル（掲載誌）
- IEICE Transactions on Electronics
- 巻号年月日等（掲載誌）
- E93-C 4
- 掲載巻
- E93-C
- 掲載号
- 4
- 掲載ページ
- 440-444
- 掲載年月日（W3CDTF）
- 2010
- ISSN（掲載誌）
- 09168524
- 出版事項（掲載誌）
- The Institute of Electronics, Information and Communication Engineers
- 本文の言語コード
- en
- 件名標目
- 対象利用者
- 一般
- 標準番号（その他）
- BIBCODE : 2010IEITE..93..440Y
- DOI
- 10.1587/transele.e93.c.440
- オンライン閲覧公開範囲
- インターネット公開
- 関連情報（URI）
- 参照
- Design of Binary Convolution Operation Circuit for Binarized Neural Networks Using Single-Flux-Quantum CircuitHigh area efficiency binary neural processing elements with time-domain signals using SFQ circuitsDesign of Max Pooling Operation Circuit for Binarized Neural Networks Using Single-Flux-Quantum CircuitImplementation of Bayesian Network Based on Ultra-High-Speed Superconductor Random Number GeneratorsEnhanced operation frequencies of bipolar double-flux-quantum amplifiers fabricated using 10 kA cm−2 Nb/AlOx/Nb integration processSuperconductor Computing for Neural NetworksStochastic matrix multiplier using superconductor single-flux-quantum circuitSmall-Area Sorting Network Based on Unary Coding Using Single Flux Quantum CircuitsHigh-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum CircuitsA Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length MatchingProposal of ultra-low voltage quantum well optical modulator for optical interconnection in superconducting integrated circuit systemsDesign of Discrete Hopfield Neural Network Using a Single Flux Quantum CircuitStatic Timing Analysis for Single-Flux-Quantum Circuits Composed of Various GatesLowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock DistributionWire Length-Matching Aware Placement Method for Rapid Single Flux Quantum Logic CircuitsEvaluation of True Random Number Sequences Generated by Utilizing Timing Jitters in Superconducting Integrated CircuitsDesign and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm$^{2}$ Nb Process100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-${\rm kA/cm}^{2}$ Niobium ProcessDemonstration of a 52-GHz Bit-Parallel Multiplier Using Low-Voltage Rapid Single-Flux-Quantum LogicAdiabatic quantum-flux-parametron with delay-line clocking: logic gate demonstration and phase skipping operationQECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface CodeInvestigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuitsFast and accurate inductance and coupling calculation for a multi-layer Nb processImprovement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias VoltageInvestigation of Timing Parameters in Single-Flux-Quantum Circuits Using Low Critical-Current Junctions and Low Bias VoltagesQULATIS: A Quantum Error Correction Methodology toward Lattice SurgeryInter-Temperature Bandwidth Reduction in Cryogenic QAOA MachinesExperimental Demonstration of 1.2-Gb/s/Channel Readout Operation of Josephson–CMOS Hybrid MemoryC3-VQA: Cryogenic Counter-Based Coprocessor for Variational Quantum AlgorithmsRapid Single-Flux-Quantum Logic Circuits Using Clockless GatesA High-Throughput Multiply-Accumulate Unit With Long Feedback Loop Using Low-Voltage Rapid Single-Flux Quantum CircuitsRSFQ 4-bit Bit-Slice Integer MultiplierDesign and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm<sup>2</sup> Nb ProcessHigh-Speed Operation of 0.25-mV RSFQ Arithmetic Logic Unit Based on 10-kA/cm<sup>2</sup> Nb Process TechnologyTowards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel ProcessorOperation of RSFQ Hardware Random Number Generator Comprising Two Josephson OscillatorsLayout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ CircuitsLarge-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path ProcessorsNb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process EvaluationCircuit Description and Design Flow of Superconducting SFQ Logic Circuits消費電力の限界に挑む超電導集積回路技術の最近の進展Design of a Neural Network Accelerator Using Single Flux Quantum Circuits for Ultrafast OperationPlanarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device EvaluationMarginX: Simple and Fast Circuit Parameter Optimization Tool for Superconductor CircuitsEvaluation of a True Random Number Generator Utilizing Timing Jitters in RSFQ Logic Circuits
- 参照
- RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systemsDesign and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, ${\rm CORE}1\beta$Research on Effective Moat Configuration for Nb Multi-Layer Device StructureA design approach to passive interconnects for single flux quantum logic circuitsHigh-Speed Demonstration of Single-Flux-Quantum Cross–Bar Switch up to 50 GHzSuperconductor digital frequency divider operating up to 750 GHzImprovement of Fabrication Process for 10-${\rm kA/cm}^{2}$ Multi-Layer Nb Integrated CircuitsA single flux quantum standard logic cell librarySFQ Propagation Properties in Passive Transmission Lines Based on a 10-Nb-Layer StructureEffects of the film thickness of a ground plane in the SFQ circuits with a dc-power layer
- 連携機関・データベース
- 国立情報学研究所 : CiNii Research
- 提供元機関・データベース
- Japan Link Center学術機関リポジトリデータベースCrossrefCiNii ArticlesCiNii ArticlesCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossrefCrossref
- NII論文ID
- 10026825076120006382470
- 要約等
- A single flux quantum (SFQ) logic cell library has been developed for the 10 kA/cm(2) Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits In the new cell library. the critical current density of Josephson junctions is increased from 2 5 kA/cm(2) to 10 kA/cm(2) compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed More than 300 cells have been designed. Including fundamental logic cells and wiring cells for passive interconnects We have measured all cells and confirmed they stably operate with wide operating margins On-chip high-speed test of the 'toggle flip-flop (TIT) cell has been performed by measuring the input and output voltages The TIT. cell at the input frequency of up to 400 GHz was confirmed to operate correctly Also. several fundamental digital circuits a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library. and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz
- 記録形式（IMT）
- application/pdf
- 一次資料へのリンクURL
- Yamanashi2010IEICE.pdf （fulltext）
- オンライン閲覧公開範囲
- インターネット公開
- 著作権情報
- Copyright(C)2010 IEICE
- 関連情報（DOI）
- 10.1587/transele.E93.C.440
- 連携機関・データベース
- 国立情報学研究所 : 学術機関リポジトリデータベース（IRDB）（機関リポジトリ）
- 提供元機関・データベース
- 横浜国立大学 : 横浜国立大学学術情報リポジトリ