一般注記This thesis presents an ultra-low-power wireless transceiver for Bluetooth Low-Energy standard. For achieving an ultra-low-power operation with a low sensitivity and a high blocker immunity of the presented transceiver, architecture considerations and key building blocks are discussed. A wide loop-bandwidth fractional-N DPLL plays a central role in the presented transceiver, i.e., a frequency modulator for the transmitter and a local oscillator, an analog-to-digital converter, a frequency and phase synchronizer for the receiver. To obtain better jitter and spur performances of the DPLL while maintaining low power operation, techniques such as the isolated constant slope digital-to-time converter and TDC gain calibration are also discussed in this thesis.
identifier:oai:t2r2.star.titech.ac.jp:50440691
コレクション(個別)国立国会図書館デジタルコレクション > デジタル化資料 > 博士論文
受理日(W3CDTF)2019-10-04T14:36:02+09:00
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