動的リコンフィギャラブルプロセッサにおける記憶回路の低消費電力化とDVFS手法の検討 (VLSI設計技術)

動的リコンフィギャラブルプロセッサにおける記憶回路の低消費電力化とDVFS手法の検討

(VLSI設計技術)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 111(450):2012.3.6・7

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Material Type: 記事
Title: 動的リコンフィギャラブルプロセッサにおける記憶回路の低消費電力化とDVFS手法の検討
Author/Editor: 早川勇輝
宇佐美公良
Series Title: VLSI設計技術
Author Heading: 早川勇輝
宇佐美公良
Alternative Title: Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 111(450):2012.3.6・7
Volume: 111
Issue: 450
Pages: 109-114
Publication date of volume/issue (W3CDTF): 2012-03
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: jpn
Subject Heading: 動的リコンフィギャラブルプロセッサ
低消費電力化
DVFS
SRAM
Dynamically Reconfigurable Processor
Low Power Technique
NDLC: ZN33
Target Audience: 一般
Report No. (Article): VLD2011-138
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 023575533
http://id.ndl.go.jp/bib/023575533
Bibliographic Record Category (NDL): 632