FPGAを用いたInhibitory Connected Pulse Coupled Neural Networkのハードウェア実装 (非線形問題)

FPGAを用いたInhibitory Connected Pulse Coupled Neural Networkのハードウェア実装

(非線形問題)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 112(389):2013.1.24・25

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Material Type: 記事
Title: FPGAを用いたInhibitory Connected Pulse Coupled Neural Networkのハードウェア実装
Author/Editor: 吉原正裕
生野壮一郎
黒川弘章
Series Title: 非線形問題
Author Heading: 吉原正裕
生野壮一郎
黒川弘章
Alternative Title: Hardware Implementation of the Inhibitory Connected Pulse Coupled Neural Network using FPGA
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 112(389):2013.1.24・25
Volume: 112
Issue: 389
Pages: 93-98
Publication date of volume/issue (W3CDTF): 2013-01
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: jpn
Subject Heading: 画像セグメンテーション
inhibitory connected pulse coupled neural network
FPGA
image segmentation
NDLC: ZN33
Target Audience: 一般
Report No. (Article): NLP2012-120
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 024261109
http://id.ndl.go.jp/bib/024261109
Bibliographic Record Category (NDL): 632