コンパイラと協調したシミュレーション精度切り換え可能なマルチコアアーキテクチャシミュレータ (集積回路)

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コンパイラと協調したシミュレーション精度切り換え可能なマルチコアアーキテクチャシミュレータ

(集積回路)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
024262924
Material type
記事
Author
田口 学豊ほか
Publisher
東京 : 電子情報通信学会
Publication date
2013
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 112(425):2013.1.31・2.1
Publication Page
p.65-71
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Paper

Material Type
記事
Author/Editor
田口 学豊
阿部 洋一
木村 啓二 他
Series Title
Alternative Title
A Parallelizing Compiler Cooperative Multicore Architecture Simulator with Changeover Mechanism of Simulation Modes
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
112(425):2013.1.31・2.1
Volume
112
Issue
425