A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs (VLSI設計技術)

A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs

(VLSI設計技術)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 112(375):2013.1.16・17

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Material Type: 記事
Title: A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
Author/Editor: Krzystof Jozwik
Shinya Honda
Masato Edahiro 他
Series Title: VLSI設計技術
Author Heading: Krzystof Jozwik
Shinya Honda
Masato Edahiro
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 112(375):2013.1.16・17
Volume: 112
Issue: 375
Pages: 135-140
Publication date of volume/issue (W3CDTF): 2013-01
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: eng
Subject Heading: SW-HW Multitasking
Dynamic Reconfiguration
Runtime Reconfiguration
FPGA
NDLC: ZN33
Target Audience: 一般
Report No. (Article): VLD2012-130
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 024263583
http://id.ndl.go.jp/bib/024263583
Bibliographic Record Category (NDL): 632