FPGAアクセラレータと高位合成系を用いた三次元ステンシル計算の実装 (コンピュータシステム)

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FPGAアクセラレータと高位合成系を用いた三次元ステンシル計算の実装

(コンピュータシステム)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
024264652
Material type
記事
Author
中村 芳大ほか
Publisher
東京 : 電子情報通信学会
Publication date
2013-01
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 112(376):2013.1.16・17
Publication Page
p.153-158
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Paper

Material Type
記事
Author/Editor
中村 芳大
土肥 慶亮
柴田 裕一郎 他
Alternative Title
Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
112(376):2013.1.16・17
Volume
112
Issue
376