RDRアーキテクチヤを対象とした時間・面積制約にもとづくフォールドセキュア高位合成手法

Journal name: 回路とシステムワークショップ論文集 Workshop on Circuits and Systems 26:2013.7.29・30

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Material Type: 記事
Title: RDRアーキテクチヤを対象とした時間・面積制約にもとづくフォールドセキュア高位合成手法
Author/Editor: 川村一志
柳澤政生
戸川望
Author Heading: 川村一志
柳澤政生
戸川望
Alternative Title: A Time and Area Constraint-based Fault-Secure High-Level Synthesis Algorithm for RDR Architectures
Periodical title: 回路とシステムワークショップ論文集 Workshop on Circuits and Systems
No. or year of volume/issue: 26:2013.7.29・30
Volume: 26
Pages: 454-459
Publication date of volume/issue (W3CDTF): 2013-07
Publication (Periodical Title): [東京] : [電子情報通信学会]
Place of Publication (Country Code): JP
Text Language Code: jpn
NDLC: ZN33
Target Audience: 一般
Holding library: 国立国会図書館
Call No.: YH247-954
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 024733692
http://id.ndl.go.jp/bib/024733692
Bibliographic Record Category (NDL): 632