回路分割機構付き高位合成ツールによる分割回路の検証手法 (コンピュータシステム)

回路分割機構付き高位合成ツールによる分割回路の検証手法

(コンピュータシステム)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114(155):2014.7.28-30

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Material Type: 記事
Title: 回路分割機構付き高位合成ツールによる分割回路の検証手法
Author/Editor: 松田和也
三好健文
竹本正志他
Series Title: コンピュータシステム
Author Heading: 松田和也
三好健文
竹本正志
Alternative Title: Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 114(155):2014.7.28-30
Volume: 114
Issue: 155
Pages: 43-48
Publication date of volume/issue (W3CDTF): 2014-07
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: jpn
Subject Heading: 高位合成
回路分割
回路検証
High Level Synthesize
HLS
Circuit Partitioning
Circuit Verification
NDLC: ZN33
Target Audience: 一般
Report No. (Article): CPSY2014-17
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 025634834
http://id.ndl.go.jp/bib/025634834
Bibliographic Record Category (NDL): 632