RISCプロセッサの内部レジスタの不揮発化に向けた書き込み削減手法 (VLSI設計技術)

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RISCプロセッサの内部レジスタの不揮発化に向けた書き込み削減手法

(VLSI設計技術)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
025635360
Material type
記事
Author
後藤 智哉ほか
Publisher
東京 : 電子情報通信学会
Publication date
2014-07
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114(123):2014.7.9-11
Publication Page
p.213-218
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Paper

Material Type
記事
Author/Editor
後藤 智哉
柳澤 政生
木村 晋二
Series Title
Alternative Title
Write Reduction of Internal Registers for Non-volatile RISC Processors
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
114(123):2014.7.9-11
Volume
114
Issue
123