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雑誌電子情報通信学会技術研究報告 : 信学技報
Volume number114(124)-114(125):2014.7.9-2014.7.11
ArticleCEGAR法を用いた...

CEGAR法を用いたLUT回路のブーリアンマッチングの高速化手法 (システム数理と応用)

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CEGAR法を用いたLUT回路のブーリアンマッチングの高速化手法

(システム数理と応用)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
025636710
Material type
記事
Author
松永 裕介
Publisher
東京 : 電子情報通信学会
Publication date
2014-07
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114(125):2014.7.9-11
Publication Page
p.201-206
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Paper

Material Type
記事
Title
CEGAR法を用いたLUT回路のブーリアンマッチングの高速化手法
Author/Editor
松永 裕介
Series Title
システム数理と応用
Author Heading
松永 裕介
Alternative Title
Accelerating Boolean Matching of LUT-based Circuits using CEGAR method
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
114(125):2014.7.9-11
Volume
114
Issue
125