演算チェイニング候補列挙に基づく配線遅延を考慮した高位合成手法

Journal name: 回路とシステムワークショップ論文集 Workshop on Circuits and Systems 27:2014.8.4・5

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Material Type: 記事
Title: 演算チェイニング候補列挙に基づく配線遅延を考慮した高位合成手法
Author/Editor: 寺田晃太朗
柳澤政生
戸川望
Author Heading: 寺田晃太朗
柳澤政生
戸川望
Alternative Title: An Interconnect-Delay-Aware High-Level Synthesis Algorithm with Operation Chainings Using Chaining Enumeration
Periodical title: 回路とシステムワークショップ論文集 Workshop on Circuits and Systems
No. or year of volume/issue: 27:2014.8.4・5
Volume: 27
Pages: 440-445
Publication date of volume/issue (W3CDTF): 2014-08
Publication (Periodical Title): [東京] : [電子情報通信学会]
Place of Publication (Country Code): JP
Text Language Code: jpn
NDLC: ZN33
Target Audience: 一般
Holding library: 国立国会図書館
Call No.: YH247-954
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 025639724
http://id.ndl.go.jp/bib/025639724
Bibliographic Record Category (NDL): 632