超低電圧0.4V動作SOTB-CMOS回路のダイ間遅延ばらつきを抑制する基板バイアス制御技術 (シリコン材料・デバイス)

Icons representing 記事

超低電圧0.4V動作SOTB-CMOS回路のダイ間遅延ばらつきを抑制する基板バイアス制御技術

(シリコン材料・デバイス)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
025917615
Material type
記事
Author
槇山 秀樹ほか
Publisher
東京 : 電子情報通信学会
Publication date
2014-10
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114(255):2014.10.16・17
Publication Page
p.61-68
View All

Holdings of Libraries in Japan

This page shows libraries in Japan other than the National Diet Library that hold the material.

Please contact your local library for information on how to use materials or whether it is possible to request materials from the holding libraries.

other

  • CiNii Research

    Search Service
    You can check the holdings of institutions and databases with which CiNii Research is linked at the site of CiNii Research.

Bibliographic Record

You can check the details of this material, its authority (keywords that refer to materials on the same subject, author's name, etc.), etc.

Paper

Material Type
記事
Author/Editor
槇山 秀樹
山本 芳樹
尾田 秀一 他
Alternative Title
Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB MOS Circuits at Ultralow-Voltage (0.4 V) Operation
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
114(255):2014.10.16・17
Volume
114
Issue
255