回路面積を考慮したS...

回路面積を考慮したSuspicious Timing Error Prediction回路の挿入位置決定手法の改良と評価 (VLSI設計技術 ; デザインガイア2014 : VLSI設計の新しい大地)

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回路面積を考慮したSuspicious Timing Error Prediction回路の挿入位置決定手法の改良と評価

(VLSI設計技術 ; デザインガイア2014 : VLSI設計の新しい大地)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
025982874
Material type
記事
Author
吉田 慎之介ほか
Publisher
東京 : 電子情報通信学会
Publication date
2014-11
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114(328):2014.11.26-28
Publication Page
p.57-62
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Paper

Material Type
記事
Author/Editor
吉田 慎之介
史 又華
柳澤 政生 他
Alternative Title
An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
114(328):2014.11.26-28
Volume
114
Issue
328