回路面積を考慮した不揮発性メモリ書き込み削減符号生成手法 (VLSI設計技術)

回路面積を考慮した不揮発性メモリ書き込み削減符号生成手法

(VLSI設計技術)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 115(338):2015.12.1-3

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Material Type: 記事
Title: 回路面積を考慮した不揮発性メモリ書き込み削減符号生成手法
Author/Editor: 多和田雅師
木村晋二
柳澤政生他
Series Title: VLSI設計技術
Author Heading: 多和田雅師
木村晋二
柳澤政生
Alternative Title: A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 115(338):2015.12.1-3
Volume: 115
Issue: 338
Pages: 249-253
Publication date of volume/issue (W3CDTF): 2015-12
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: jpn
Subject Heading: 不揮発性メモリ
書き込み削減
符号化
Non-volatile memory
Writing-reduction code
Encoding/decoding
NDLC: ZN33
Target Audience: 一般
Report No. (Article): VLD2015-76
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 027038446
http://id.ndl.go.jp/bib/027038446
Bibliographic Record Category (NDL): 632