後方順序的クロックゲーティング自動挿入のための制御信号抽出手法 (VLSI設計技術)

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後方順序的クロックゲーティング自動挿入のための制御信号抽出手法

(VLSI設計技術)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
027107280
Material type
記事
Author
後藤 智哉ほか
Publisher
東京 : 電子情報通信学会
Publication date
2016-01
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 115(398):2016.1.19-21
Publication Page
p.97-102
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Paper

Material Type
記事
Author/Editor
後藤 智哉
柳澤 政生
木村 晋二
Series Title
Alternative Title
Control Signal Extraction for Backward Sequential Clock Gating
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
115(398):2016.1.19-21
Volume
115
Issue
398