SATソルバによるCMOS回路のレイアウト面積最小化手法

Journal name: 回路とシステムワークショップ論文集 Workshop on Circuits and Systems 28:2015.8.3・4

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Material Type: 記事
Title: SATソルバによるCMOS回路のレイアウト面積最小化手法
Author/Editor: 増子駿
小平行秀
Author Heading: 増子駿
小平行秀
Alternative Title: Area Minimization Method for Layout of CMOS Circuits Using SAT-Solver
Periodical title: 回路とシステムワークショップ論文集 Workshop on Circuits and Systems
No. or year of volume/issue: 28:2015.8.3・4
Volume: 28
Pages: 237-242
Publication date of volume/issue (W3CDTF): 2015-08
Publication (Periodical Title): [東京] : [電子情報通信学会]
Place of Publication (Country Code): JP
Text Language Code: jpn
NDLC: ZN33
Target Audience: 一般
Holding library: 国立国会図書館
Call No.: YH247-954
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 027260204
http://id.ndl.go.jp/bib/027260204
Bibliographic Record Category (NDL): 632