MERP-CNN : A memory-efficient reconfigurable processor for convolutional neural networks based on FPGA (VLSI設計技術)

MERP-CNN : A memory-efficient reconfigurable processor for convolutional neural networks based on FPGA

(VLSI設計技術)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116(21):2016.5.11

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Material Type: 記事
Title: MERP-CNN : A memory-efficient reconfigurable processor for convolutional neural networks based on FPGA
Author/Editor: Xushen HAN
Dajiang ZHOU
Shinji KIMURA
Series Title: VLSI設計技術
Author Heading: Xushen HAN
Dajiang ZHOU
Shinji KIMURA
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 116(21):2016.5.11
Volume: 116
Issue: 21
Pages: 47-52
Publication date of volume/issue (W3CDTF): 2016-05-11
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: eng
Subject Heading: convolutional neural network
memory-efficient
multiboot
NDLC: ZN33
Target Audience: 一般
Report No. (Article): VLD2016-5
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 027374527
http://id.ndl.go.jp/bib/027374527
Bibliographic Record Category (NDL): 632