ビアスイッチFPGA向け配線解析手法の検討 (VLSI設計技術)

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ビアスイッチFPGA向け配線解析手法の検討

(VLSI設計技術)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
028877383
Material type
記事
Author
中澤 祐希ほか
Publisher
東京 : 電子情報通信学会
Publication date
2018
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 117(455):2018.2.28-3.2
Publication Page
p.187-192
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Paper

Material Type
記事
Author/Editor
中澤 祐希
土井 龍太郎
劉 載勲
橋本 昌宜
Series Title
Alternative Title
A Study on Interconnect Delay Computation for Via-switch Based FPGA
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
117(455):2018.2.28-3.2
Volume
117
Issue
455