算盤アーキテクチャを用いた10進加算器とその剰余演算への応用 (ディペンダブルコンピューティング)

算盤アーキテクチャを用いた10進加算器とその剰余演算への応用

(ディペンダブルコンピューティング)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 108(431) 2009.2.16

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Material Type: 記事
Title: 算盤アーキテクチャを用いた10進加算器とその剰余演算への応用
Author/Editor: 飯島唯仁
魏書剛
Series Title: ディペンダブルコンピューティング
Author Heading: 飯島唯仁
魏書剛
Alternative Title: Decimal adder using abacus architecture and its application to residue arithmetic
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 108(431) 2009.2.16
Volume: 108
Issue: 431
Pages: 19～23
Publication date of volume/issue (W3CDTF): 2009-02-16
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: jpn
Subject Heading: 算盤
10進加算
剰余数系
VHDL
synopsys
abacus
decimal addition
residue number system
NDLC: ZN33
Target Audience: 一般
Report No. (Article): DC2008-71
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 10175021
http://id.ndl.go.jp/bib/10175021
Bibliographic Record Category (NDL): 632