VHDLによる3層階層型ニューラルネットのFPGA実装--パターン認識デバイスの設計 (ニューロコンピューティング)

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VHDLによる3層階層型ニューラルネットのFPGA実装--パターン認識デバイスの設計

(ニューロコンピューティング)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
10247342
Material type
記事
Author
長尾 忠俊ほか
Publisher
東京 : 電子情報通信学会
Publication date
2009-05
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 109(53) 2009.5.25・26
Publication Page
p.1~6
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Paper

Material Type
記事
Author/Editor
長尾 忠俊
水上 郁太朗
本田 達矢 他
Alternative Title
An implementation of artificial Neural Network on FPGA by VHDL: design pattern recognition device
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
109(53) 2009.5.25・26
Volume
109
Issue
53