多重高速保存型一括並列処理による省メモリな音声認識用HMM計算回路 (ディペンダブルコンピューティング)

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多重高速保存型一括並列処理による省メモリな音声認識用HMM計算回路

(ディペンダブルコンピューティング)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
11047178
Material type
記事
Author
島崎 亮ほか
Publisher
東京 : 電子情報通信学会
Publication date
2011-03
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 110(474) 2011.3.18・19
Publication Page
p.225~230
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Paper

Material Type
記事
Author/Editor
島崎 亮
中村 一博
高木 一義 他
Alternative Title
Memory efficient VLSI architecture of output probability and likelihood score computations for HMM-based word recognition using multiple fast store-based block parallel processing
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
110(474) 2011.3.18・19
Volume
110
Issue
474