多重並列グループ署名の低消費電力回路アーキテクチャ (VLSI設計技術)

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多重並列グループ署名の低消費電力回路アーキテクチャ

(VLSI設計技術)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
11048060
Material type
記事
Author
森岡 澄夫ほか
Publisher
東京 : 電子情報通信学会
Publication date
2011-03
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 110(432) 2011.3.2-4
Publication Page
p.69~74
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Paper

Material Type
記事
Author/Editor
森岡 澄夫
古川 潤
佐古 和恵
Series Title
Alternative Title
A low-power hardware architecture for parallel group signature computation
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
110(432) 2011.3.2-4
Volume
110
Issue
432