ゲートレベルシミュレーションによるエラー検出・回復方式回路の評価 (VLSI設計技術)

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ゲートレベルシミュレーションによるエラー検出・回復方式回路の評価

(VLSI設計技術)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
11048256
Material type
記事
Author
井上 雅文ほか
Publisher
東京 : 電子情報通信学会
Publication date
2011-03
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 110(432) 2011.3.2-4
Publication Page
p.147~152
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Paper

Material Type
記事
Author/Editor
井上 雅文
右近 祐太
高橋 篤司
Series Title
Alternative Title
An evaluation of error detection/correction circuits by gate level simulation
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
110(432) 2011.3.2-4
Volume
110
Issue
432