二段階検証による順序回路の限定モデル検査の高速化手法 (VLSI設計技術)

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二段階検証による順序回路の限定モデル検査の高速化手法

(VLSI設計技術)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
11048277
Material type
記事
Author
尾野 紀博ほか
Publisher
東京 : 電子情報通信学会
Publication date
2011-03
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 110(432) 2011.3.2-4
Publication Page
p.159~164
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Paper

Material Type
記事
Author/Editor
尾野 紀博
中村 一博
高木 一義 他
Series Title
Alternative Title
Acceleration of bounded model checking for sequential circuits with two-phase verification
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
110(432) 2011.3.2-4
Volume
110
Issue
432