3次元集積化技術を利用した高スループットコンピューティング向け1Tbyte/s 1GbitマルチコアDRAMアーキテクチャ (集積回路)

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3次元集積化技術を利用した高スループットコンピューティング向け1Tbyte/s 1GbitマルチコアDRAMアーキテクチャ

(集積回路)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
11069649
Material type
記事
Author
小埜 和夫ほか
Publisher
東京 : 電子情報通信学会
Publication date
2011-04
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 111(6) 2011.4.18・19
Publication Page
p.81~86
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Paper

Material Type
記事
Author/Editor
小埜 和夫
柳川 善光
小田部 晃 他
Series Title
Alternative Title
1-Tbyte/s 1-Gbit multicore DRAM architecture using 3-D integration for high-throughput computing
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
111(6) 2011.4.18・19
Volume
111
Issue
6