1桁2ビット/3ビット混合表現を用いた高速冗長2進加減算器

Journal name: 電気学会論文誌. C, 電子・情報・システム部門誌 = IEEJ transactions on electronics, information and systems 121(4) 2001.4

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Material Type: 記事
Title: 1桁2ビット/3ビット混合表現を用いた高速冗長2進加減算器
Author/Editor: 日野杉充希
恒川佳隆
三浦守
Author Heading: 日野杉充希
恒川佳隆
三浦守
Periodical title: 電気学会論文誌. C, 電子・情報・システム部門誌 = IEEJ transactions on electronics, information and systems
No. or year of volume/issue: 121(4) 2001.4
Volume: 121
Issue: 4
Pages: 733～741
Publication date of volume/issue (W3CDTF): 2001-04
ISSN (Periodical Title): 0385-4221
ISSN-L (Periodical Title): 0385-4221
Publication (Periodical Title): 東京 : 電気学会
Place of Publication (Country Code): JP
Text Language Code: jpn
Subject Heading: 冗長2進表現
VLSI評価
NDLC: ZN31
Target Audience: 一般
Holding library: 国立国会図書館
Call No.: Z16-795
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 5725705
http://id.ndl.go.jp/bib/5725705
Bibliographic Record Category (NDL): 632