システムVLSIのための高位面積/遅延/消費電力見積もりに基づく低消費電力指向高位合成手法

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 101(577) 2002.1.24

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Material Type: 記事
Title: システムVLSIのための高位面積/遅延/消費電力見積もりに基づく低消費電力指向高位合成手法
Author/Editor: 野田真一
柳澤政生
大附辰夫他
Author Heading: 野田真一
柳澤政生
大附辰夫
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 101(577) 2002.1.24
Volume: 101
Issue: 577
Pages: 93～100
Publication date of volume/issue (W3CDTF): 2002-01-24
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: jpn
Subject Heading: 低消費電力化
順序回路
電源電圧
演算器交換
Gated Clock
High-level synthesis
power reduction
sequential circuits
supply voltage
exchange of functional units
gated clocks
NDLC: ZN33
Target Audience: 一般
Report No. (Article): VLD2001-144
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 6073021
http://id.ndl.go.jp/bib/6073021
Bibliographic Record Category (NDL): 632