Secure Processor Architecture for High-Speed Verification of Memory Integrity

Journal name: 情報処理学会研究報告 = IPSJ SIG technical reports 2006(127) 2006.11.28-30

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Material Type: 記事
Title: Secure Processor Architecture for High-Speed Verification of Memory Integrity
Author/Editor: Atsuya Okazaki
Masaki Nakanishi
Shigeru Yamashita
Author Heading: Atsuya Okazaki
Masaki Nakanishi
Shigeru Yamashita
Periodical title: 情報処理学会研究報告 = IPSJ SIG technical reports
No. or year of volume/issue: 2006(127) 2006.11.28-30
Volume: 2006
Issue: 127
Pages: 13～18
Publication date of volume/issue (W3CDTF): 2006-11
ISSN (Periodical Title): 0919-6072
ISSN-L (Periodical Title): 0919-6072
Publication (Periodical Title): 東京 : 情報処理学会
Place of Publication (Country Code): JP
Text Language Code: eng
NDLC: ZM13
Target Audience: 一般
Report No. (Article): 2006-ARC-170-(3)
Holding library: 国立国会図書館
Call No.: Z14-1121
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 8571165
http://id.ndl.go.jp/bib/8571165
Bibliographic Record Category (NDL): 632