交流電界印加時の電流テストによるCMOS LSIのリード浮き検出のための印加交流電圧

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交流電界印加時の電流テストによるCMOS LSIのリード浮き検出のための印加交流電圧

Call No. (NDL)
Z74-B258
Bibliographic ID of National Diet Library
8814737
Material type
記事
Author
高木 正夫ほか
Publisher
東京 : エレクトロニクス実装学会
Publication date
2007-05
Material Format
Paper
Journal name
エレクトロニクス実装学会誌 = Journal of the Japan Institute of Electronics Packaging 10(3) (通号 65) 2007.5
Publication Page
p.219~228
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Paper

Material Type
記事
Author/Editor
高木 正夫
橋爪 正樹
一宮 正博 他
Alternative Title
Applied AC voltage for detecting open leads of CMOS LSI by monitoring supply current under AC electric field
Periodical title
エレクトロニクス実装学会誌 = Journal of the Japan Institute of Electronics Packaging
No. or year of volume/issue
10(3) (通号 65) 2007.5
Volume
10
Issue
3
Sequential issue number
65