9つのCPUと2つのマトリクスプロセッサを搭載したマルチコアSoCの開発 (集積回路)

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9つのCPUと2つのマトリクスプロセッサを搭載したマルチコアSoCの開発

(集積回路)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
8896171
Material type
記事
Author
中島 雅美ほか
Publisher
東京 : 電子情報通信学会
Publication date
2007-08
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 107(195) 2007.8.23・24
Publication Page
p.1~4
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Paper

Material Type
記事
Author/Editor
中島 雅美
石見 幸一
藤原 隼人 他
Series Title
Alternative Title
Development of a multi-core SoC with 9 CPUs and 2 matrix processors
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
107(195) 2007.8.23・24
Volume
107
Issue
195