PLL,DLL技術にみる高性能化動向 (集積回路)

PLL,DLL技術にみる高性能化動向

(集積回路)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 107(195) 2007.8.23・24

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Material Type: 記事
Title: PLL,DLL技術にみる高性能化動向
Author/Editor: 道正志郎
Series Title: 集積回路
Author Heading: 道正志郎
Alternative Title: Design trends of high performance PLLs and DLLs
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 107(195) 2007.8.23・24
Volume: 107
Issue: 195
Pages: 23～28
Publication date of volume/issue (W3CDTF): 2007-08
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: jpn
Subject Heading: 位相同期回路
遅延同期回路
ループフィルタ
アダプティブバイアス
分数分周器
Phase Locked Loops
Delay Locked Loops
Loop Filter
Adaptive Biasing
Fractional Divider
NDLC: ZN33
Target Audience: 一般
Report No. (Article): ICD2007-73
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 8896190
http://id.ndl.go.jp/bib/8896190
Bibliographic Record Category (NDL): 632