Checker circuit generation for System Verilog Assertions in prototyping verification (VLSI設計技術)

Checker circuit generation for System Verilog Assertions in prototyping verification

(VLSI設計技術)

Journal name: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 108(22) 2008.5.8

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Material Type: 記事
Title: Checker circuit generation for System Verilog Assertions in prototyping verification
Author/Editor: Mengru Wang
木村晋二
Series Title: VLSI設計技術
Author Heading: Mengru Wang
木村晋二
Periodical title: 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue: 108(22) 2008.5.8
Volume: 108
Issue: 22
Pages: 7～12
Publication date of volume/issue (W3CDTF): 2008-05-08
ISSN (Periodical Title): 0913-5685
ISSN-L (Periodical Title): 0913-5685
Publication (Periodical Title): 東京 : 電子情報通信学会
Place of Publication (Country Code): JP
Text Language Code: eng
Subject Heading: Assertion-Based Verification
System Verilog Assertion
NDLC: ZN33
Target Audience: 一般
Report No. (Article): VLD2008-2
Holding library: 国立国会図書館
Call No.: Z16-940
Data Provider (Database): 国立国会図書館 : 国立国会図書館雑誌記事索引
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 9526715
http://id.ndl.go.jp/bib/9526715
Bibliographic Record Category (NDL): 632