レイテンシ削減を目的としたフロアプラン指向FPGA向け高位合成手法に関する研究

Notes on use

Search by Bookstore

This page shows libraries in Japan other than the National Diet Library that hold the material.

Please contact your local library for information on how to use materials or whether it is possible to request materials from the holding libraries.

other

Waseda University Repository
Digital
You can check the holdings of institutions and databases with which Institutional Repositories DataBase(IRDB)(Institutional Repository) is linked at the site of Institutional Repositories DataBase(IRDB)(Institutional Repository).
Waseda University Repository

You can check the details of this material, its authority (keywords that refer to materials on the same subject, author's name, etc.), etc.

Material Type: 博士論文
Title: レイテンシ削減を目的としたフロアプラン指向FPGA向け高位合成手法に関する研究
Author/Editor: Fujiwara, Koichi
藤原, 晃一
Author Heading: Fujiwara, Koichi
藤原, 晃一
Publication Date: 2018
Publication Date (W3CDTF): 2018
Alternative Title: Floorplan-driven High-level Synthesis Algorithms for Latency Reduction Targeting FPGA Designs
Pages: 1-120
Degree grantor/type: 早稲田大学
Date Granted: 2019-03-15
Dissertation Number: 甲第5714号
Degree Type: 博士(工学)
Text Language Code: jpn
Target Audience: 一般
Note (General): 早大学位記番号:新8126
Format (IMT): application/pdf
Source: Honbun-8126.pdf （fulltext）
https://waseda.repo.nii.ac.jp/record/46641/files/Honbun-8126.pdf
Access Restrictions: インターネット公開
Data Provider (Database): 国立情報学研究所 : 学術機関リポジトリデータベース（IRDB）（機関リポジトリ）
https://irdb.nii.ac.jp
Original Data Provider (Database): 早稲田大学 : 早稲田大学リポジトリ