La-silicateゲート絶縁膜の薄膜化を可能とする微結晶金属ゲート電極の研究

• Material Type: 博士論文
• Title: La-silicateゲート絶縁膜の薄膜化を可能とする微結晶金属ゲート電極の研究
• Author/Editor: TUOKEDAERHAN, KAMALE
• Author Heading: TUOKEDAERHAN, KAMALE
• Publication Date: 2014-03
• Publication Date (W3CDTF): 2014-03
• Alternative Title: A Study on Metal Gate Electrodes with Nano-Sized Grains for Scalable La-silicate Gate Dielectrics
• Degree grantor/type: 東京工業大学
• Date Granted: 2014-03-26
• Dissertation Number: 甲第9536号
• Degree Type: 博士(工学)
• Text Language Code: eng
• Subject Heading: La-silicate, metal gate, tungsten carbide, interface state denisity, grain size,roughness
• Target Audience: 一般
• Note (General): Downscaling of the MOSFET has been the driving force for circuit evolution. Feature size of MOSFET becomes smaller and smaller, billions of CMOS transistors are integrated on a single chip. However, power consumption caused by leakage current increased to unacceptable level. Therefore, new materials and new structures in MOSFET have been introduced to solve these issues. High-k gate dielectrics have enabled continuous scaling in CMOS devices by increasing the capacitive coupling of gate electrode to the channel which eventually suppresses the short channel effects, while reducing the gate leakage current. Considering further equivalent oxide thickness (EOT) scaling down to 0.45 nm, which is required in the year of 2026 from ITRS roadmap, high-k materials should be directly in contact with Si channels. Some of attempts to achieve direct contact of high-k on Si channels have been proposed so far; those include precise oxygen partial pressure controlled process and a thermal process to reduce the interfacial layer by incorporating additional elements in the metal gates. In addition to these processes, La-silicate can be in direct contact with Si channels by means of silicate reactions between La2O3 layer and Si channel. The prominent features of La-silicate are that the structure is amorphous and the silicate reaction does not show any channel surface orientation dependency, which are advantageous for scaled devices with three dimensional channels. Issues in La-silicate/Si interfaces include Dit in the order of high 1011 cm-2/eV, and interface roughness presented at both metal/La-silicate and La-silicate/Si interfaces, which results in channel mobility degradation due to La-silicate thickness variation. An experimental work has shown that metal gate materials affect the interface properties, so the impact of metal gate should be clarified. According to reports, the crystal structure and grain size of metal gates strongly impact on electrical properties of MOS devices, in terms of threshold voltage variability, metal gates with grain less than 5nm or amorphous are preferable. Therefore, in this study, metal gate electrodes with nano-sized grains for scalable La-silicate gate dielectrics were experimentally investigated. Novel sputtering processes have been introduced to form nano-sized metal gate. Multi-stacking of carbon and metal thin films with subsequent annealing process to reactively form metal carbides (TiC, TaC and W2C) has been presented. Grain sizes of the carbides are as small as 3.9, 3.2, and 1.9 nm for TiC, TaC and W2C, respectively. Work functions of TiC, TaC and W2C layers have been extracted as 4.3, 4.7, and 4.9 eV, respectively, relatively high values owing to oriented growth. W2C layer formed by the presented process gives high potential to gate electrode application in terms of grian size and oriented growth for scaled devices.Electrical properties of La-silicate MOS devices and nMOSFET with nano-sized tungsten carbide (W2C) gate electrode has been experimentally investigated. Interface state density (Dit) was suppressed by W2C gate electrodes. Atomically flat metal/high-k and high-k/Si interfaces can be achieved by W2C gate electrodes, where the interface roughness extracted from TEM is 0.26 and 0.12nm, respectively. Origin of interface state density is due to La-silicate/Si interface roughness due to grains in metal gate electrode. Electron eff showed improvements in both low and high Eeff, especially 163 cm2/Vs (Eeff=1MV) at an EOT of 0.63 nm was achieved, owing to lower Dit and reduced roughness scatterings.Reliability of La-silicate with different gate electrodes, such as tungsten carbide and tungsten, was measured by TDDB and PBTI. Better reliability was obtained by nano sized W2C gate electrode owing to atomically flat high-k/Si interface.; identifier:oai:t2r2.star.titech.ac.jp:50231543
• Format (IMT): application/pdf
• Source: http://t2r2.star.titech.ac.jp/rrws/file/CTT100667410/ATD100000413/thesis_11D36103_Kamale Tuokedaerhan.pdf （fulltext）; http://t2r2.star.titech.ac.jp/rrws/file/CTT100667410/ATD100000413/thesis_11D36103_Kamale%20Tuokedaerhan.pdf
• Access Restrictions: インターネット公開
• Data Provider (Database): 国立情報学研究所 : 学術機関リポジトリデータベース（IRDB）（機関リポジトリ）; https://irdb.nii.ac.jp
• Original Data Provider (Database): 東京工業大学 : 東京工業大学リサーチリポジトリ