FPGAとOpenCLによる高性能計算

Material type: 博士論文

Author: ZOHOURI, Hamid Reza

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Publication date: 2018-09

Material Format: Digital

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Name of awarding university/degree: 東京工業大学,博士(学術)

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Note (General)：: In this work we evaluate the potential of FPGAs for accelerating HPC workloads as a more power-efficient alternative to GPUs. Using High-Level Synthes...

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Material Type: 博士論文
Title: FPGAとOpenCLによる高性能計算
Author/Editor: ZOHOURI, Hamid Reza
Author Heading: ZOHOURI, Hamid Reza
Publication Date: 2018-09
Publication Date (W3CDTF): 2018-09
Alternative Title: High Performance Computing with FPGAs and OpenCL
Degree grantor/type: 東京工業大学
Date Granted: 2018-09-20
Dissertation Number: 甲第11010号
Degree Type: 博士(学術)
Text Language Code: eng
Subject Heading: FPGA, OpenCL, HPC, Stencil
Target Audience: 一般
Note (General): In this work we evaluate the potential of FPGAs for accelerating HPC workloads as a more power-efficient alternative to GPUs. Using High-Level Synthesis and a large set of optimization techniques, we show that FPGAs can achieve better performance than CPUs, and better power efficiency than both CPUs and GPUs for typical HPC workloads. Furthermore, we show that for the specific case of stencil computation, the unique architectural advantages of FPGAs allow them to surpass high-end CPU, Xeon Phi and GPU devices. Unlike previous work, our FPGA-based stencil accelerator combines spatial blocking with temporal blocking to achieve high performance without restricting input size. With support for high-order stencils, we achieve the highest single-FPGA performance for 2D and 3D stencil computation of any order, to this day.
identifier:oai:t2r2.star.titech.ac.jp:50420964
Format (IMT): application/pdf
Source: fulltext
http://t2r2.star.titech.ac.jp/rrws/file/CTT100770460/ATD100000413/thesis_15D54042_Hamid_Reza_ZOHOURI.pdf
Access Restrictions: インターネット公開
Data Provider (Database): 国立情報学研究所 : 学術機関リポジトリデータベース（IRDB）（機関リポジトリ）
https://irdb.nii.ac.jp
Original Data Provider (Database): 東京工業大学 : 東京工業大学リサーチリポジトリ