Study of Design Methodology of ASIC and FPGA Considering Correlation between Process Variation and BTI-Induced Degradation

• Material Type: 博士論文
• Title: Study of Design Methodology of ASIC and FPGA Considering Correlation between Process Variation and BTI-Induced Degradation
• Author/Editor: Yabuuchi, Michitarou
• Author Heading: Yabuuchi, Michitarou
• Publication Date: 2015-03-25
• Publication Date (W3CDTF): 2015-03-25
• Alternative Title: プロセスばらつきとBTIによる劣化を考慮したASIC及びFPGA設計手法に関する研究
• Degree grantor/type: 京都工芸繊維大学
• Date Granted: 2015-03-25
• Dissertation Number: 甲第742号
• Degree Type: 博士（工学）
• Text Language Code: eng
• Subject Heading: Reliability; electronics; bias temperature instability; BTI; process variation; large scale integration; LSI; design; reliability-aware design; circuit; simulation; analysis; degradation; prediction; BTI-aware netlist; ASIC; FPGA; MOSFET; Atomistic Trap-Based Model; Reaction-Diffusion Model
• Target Audience: 一般
• Note (General): type:Thesis; We widely use LSIs (Large Scale Integrations) for many industrial products such as computers, mobile devices, automobiles, and medical instruments. LSIs are infrastructures for our current advanced information society. Hundreds of millions of transistors are integrated within a single chip through advances in the scaling. The progress of the scaling improves the economic development. LSIs play important roles in our society. LSIs must be reliable products. Reliability issues of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), such as BTI (Bias Temperature Instability) and process variations become dominant at the highly-scaled process. BTI is one of the most significant aging-degradations on LSIs. Threshold voltages of transistors are shifted by BTI for the long-term period of use. They result in circuit delays and unstable performances because their effects are not negligible and avoidable. In this study, the design methodology considering the correlation between process variations and BTI-induced degradations is proposed. The design margins of LSIs are reduced without threatening their reliability. The frequencies of ROs (ring oscillators) on ASICs and FPGAs are measured to analyze the reliability issues. The frequencies are varied by the process variations according to locations on the test chips. They follow the Gaussian distribution. The groups of the highest, average and lowest frequencies are focused on. The aging-degradations of the three groups are measured on the accelerated test. The correlation between process variations and BTI-induced degradations are examined. The degradation at the highest frequency group is larger than one at the slowest frequency group. The appropriate design margins are defined according to this nature.
• Format (IMT): application/pdf
• Access Restrictions: インターネット公開
• Data Provider (Database): 国立情報学研究所 : 学術機関リポジトリデータベース（IRDB）（機関リポジトリ）; https://irdb.nii.ac.jp
• Original Data Provider (Database): 京都工芸繊維大学 : ＫＩＴ学術成果コレクション

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http://repository.lib.kit.ac.jp/repo/repository/10212/2260/D1-0742_h1.pdf fulltext

http://repository.lib.kit.ac.jp/repo/repository/10212/2260/D1-0742.pdf fulltext