SDRAMをメインメモリとするMIPS-CPUのFPGA化

Material type: 文書・図像類

Author: 森川, 良ほか

Publisher: 愛知工業大学

Publication date: 2005-03-31

Material Format: Digital

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Note (General)：: In the year of 2003, our laboratory designed CPU of MIPS architecture, one of the representative RISC architectures, in order to study design methodol...

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Material Type: 文書・図像類
Title: SDRAMをメインメモリとするMIPS-CPUのFPGA化
Author/Editor: 森川, 良
堀田, 厚生
Author Heading: 森川, 良
堀田, 厚生
Publication, Distribution, etc.: 愛知工業大学
Publication Date: 2005-03-31
Publication Date (W3CDTF): 2005-03-31
Alternative Title: FPGA implementation of MIPS CPU with SDRAM as a main memory
Periodical title: 愛知工業大学研究報告. B, 専門関係論文集 = Bulletin of Aichi Institute of Technology. Part B
No. or year of volume/issue: 40
Volume: 40
Pages: 47-52
ISSN (Periodical Title): ISSN : 0387-0812
Text Language Code: jpn
Target Audience: 一般
Note (General): In the year of 2003, our laboratory designed CPU of MIPS architecture, one of the representative RISC architectures, in order to study design methodology of a CPU, and implemented it in FPGA. The CPU adopted SRAMs in the FPGA as a main memory. As a next step, a MIPS-CPU with a SDRAM as a main memory has been studied. SDRAM controller module has been designed to cope with the specific features of SDRAMs such as refreshing, address multiplexing, access latency and so on. Designed CPU module has been impemented in a FPGA. The highest operation frequency is found to be 82.50MHz with a program of small steps.
identifier:http://repository.aitech.ac.jp/dspace/handle/11133/1242
Format (IMT): application/pdf
Source: http://repository.aitech.ac.jp/dspace/bitstream/11133/1242/1/%e7%b4%80%e8%a6%8140%e5%8f%b7B%28P47-52%29.pdf
http://repository.aitech.ac.jp/dspace/bitstream/11133/1242/1/%e7%b4%80%e8%a6%8140%e5%8f%b7B%28P47-52%29.pdf
Access Restrictions: 限定公開
Data Provider (Database): 国立情報学研究所 : 学術機関リポジトリデータベース（IRDB）（機関リポジトリ）
https://irdb.nii.ac.jp
Original Data Provider (Database): 愛知工業大学 : 愛知工業大学学術情報リポジトリ