Threshold logic: a synthesis approach [by] Michael L. Dertouzos. (Research monograph no. 32)

Threshold logic: a synthesis approach [by] Michael L. Dertouzos.

(Research monograph no. 32)

Notes on use

Note (General)：: "Modified version of Report ESL-R-200 of the Electronic Systems Laboratory of the Massachusetts Institute of Technology."

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Material Type: 図書
Title: Threshold logic: a synthesis approach [by] Michael L. Dertouzos.
Series Title: Research monograph no. 32
Title Heading: M.I.T. Press research monographs ; no. 32.
Author Heading: Dertouzos, Michael L ( 00465539 )Authorities
Publication, Distribution, etc.: Cambridge : M.I.T. Press
Publication Date: [1965]
Publication Date (W3CDTF): 1965
Extent: xii, 256 p. illus. 25 cm.
Place of Publication (Country Code): US
Text Language Code: eng
Subject Heading: Threshold logic.
Electronic digital computers -- Circuits.
LCC: QA401
DDC: 621.381
621.381952
Note (General): "Modified version of Report ESL-R-200 of the Electronic Systems Laboratory of the Massachusetts Institute of Technology."
Note (Bibliography): Bibliography: p. 249-252.
Holding library: 国立国会図書館
Call No.: 621.381-D438t
Data Provider (Database): 国立国会図書館 : 国立国会図書館蔵書
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 000006169294
http://id.ndl.go.jp/bib/000006169294
LC Control Number: 65022248 //r852
https://lccn.loc.gov/65022248
Bibliographic Record Category (NDL): 211