Latency reduction techniques in chip multiprocessor cache systems

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Material Type: 博士論文
Title: Latency reduction techniques in chip multiprocessor cache systems
Author/Editor: Michael Zhang.
Author Heading: Zhang, Michael.
Publication, Distribution, etc.: Cambridge : Massachusetts Institute of Technology
Publication Date: 2006.
Extent: 122 p.
Degree grantor/type: Massachusetts Institute of Technology
Date Granted: 2006.
Date Granted (W3CDTF): 2006
Note (Dissertation): 博士論文
Thesis (doctoral) --Massachusetts Institute of Technology, 2006.
Place of Publication (Country Code): US
Text Language Code: eng
Note (Bibliography): Includes bibliographies.
Holding library: 国立国会図書館
Call No.: M-DIMIT-06-312
Data Provider (Database): 国立国会図書館 : 国立国会図書館蔵書
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 000009305469
http://id.ndl.go.jp/bib/000009305469
Bibliographic Record Category (NDL): 216