Systematic architecture exploration method for low power and high performance reconfigurable processors

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Material Type: 博士論文
Title: Systematic architecture exploration method for low power and high performance reconfigurable processors
Author/Editor: Ittetsu Taniguchi [著]
Author Heading: 谷口, 一徹タニグチ, イッテツ
Publication, Distribution, etc.: [Ittetsu Taniguchi]
Publication Date: [2009]
Publication Date (W3CDTF): 2009
Extent: 1冊
Alternative Title: 低消費電力で高性能な再構成可能プロセッサのためのアーキテクチャの系統的探索手法テイショウヒデンリョクデコウセイノウナサイコウセイカノウプロセッサノタメノアーキテクチャノケイトウテキタンサクシュホウ
Degree grantor/type: 大阪大学
Date Granted: 平成21年3月24日
Date Granted (W3CDTF): 2009
Dissertation Number: 甲第13544号
Degree Type: 博士 (情報科学)
Note (Dissertation): 博士論文
Place of Publication (Country Code): JP
Text Language Code: eng
NDLC: UT51
Note (General): 博士論文
Holding library: 国立国会図書館
Call No.: UT51-2009-C482
Data Provider (Database): 国立国会図書館 : 国立国会図書館蔵書
https://ndlsearch.ndl.go.jp
Bibliographic ID (NDL): 000010261024
http://id.ndl.go.jp/bib/000010261024
Bibliographic Record Category (NDL): 213