Integrated circuit and system design : power and timing modeling, optimization, and simulation : 21st international workshop, PATMOS 2011 : Madrid, Spain, September 26-29, 2011 : proceedings : PATMOS meeting : Sep 2011, Madrid, Spain.

• Material Type: 図書
• ISBN: 9783642241543 (e-ISBN); 9783642241536 (soft cover : alk. paper)
• ISSN: 16113349 (e-ISSN)
• ISSN (series): 03029743
• Title: Integrated circuit and system design : power and timing modeling, optimization, and simulation : 21st international workshop, PATMOS 2011 : Madrid, Spain, September 26-29, 2011 : proceedings : PATMOS meeting : Sep 2011, Madrid, Spain.
• Series Title: Lecture Notes in Computer Science ; 6951
• Title Heading: Lecture notes in computer science ; 6951.; LNCS sublibrary. SL 1, Theoretical computer science and general issues.
• Author Heading: PATMOS 2011 (2010 : Madrid, Spain); Ayala, Jose L.; Universidad Complutense de Madrid. Dept. of Computer Architecture.
• Publication, Distribution, etc.: New York : Springer
• Publication Date: c2011.
• Publication Date (W3CDTF): 2011
• Extent: xi, 352 p.
• Other physical details: ill.
• Size: 24 cm.
• Place of Publication (Country Code): US
• Text Language Code: eng
• Genre/Form Terms: Electronic books.
• Subject Heading: Integrated circuits--Design and construction--Congresses.; Integrated circuits--Testing--Congresses.; Computers--Power supply--Congresses.; Computer-aided design--Congresses.
• LCC: TK7874
• NDLC: M17
• Target Audience: 一般
• Note (General): Papers.
• Note (Bibliography): Includes bibliographical references and author index.
• Source: ebrary; http://site.ebrary.com/id/10501513
• Holding library: 国立国会図書館
• Call No.: M17-12-1311
• Data Provider (Database): 国立国会図書館 : 国立国会図書館蔵書; https://ndlsearch.ndl.go.jp
• Bibliographic ID (NDL): 000011304211; http://id.ndl.go.jp/bib/000011304211
• OCLC No.: 763160286; https://www.worldcat.org/oclc/763160286
• Cataloging Rule: Anglo-American Cataloging Rules
• Bibliographic Record Category (NDL): 215