図書

実習Verilog‐HDL論理回路設計 : EDAツールを使ってFPGAに回路を実装する

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実習Verilog‐HDL論理回路設計 : EDAツールを使ってFPGAに回路を実装する

Material type
図書
Author
木村真也著
Publisher
CQ出版
Publication date
2001.11
Material Format
Paper
Capacity, size, etc.
24cm
NDC
548.2
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Notes on use

Note (General):

付属資料: CD-ROM (1枚 ; 12cm)参考文献・設計ツール関連URL: p270

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Paper

Material Type
図書
ISBN
4789833569
Title Transcription
ジッシュウ Verilog HDL ロンリ カイロ セッケイ : EDA ツール オ ツカッテ FPGA ニ カイロ オ ジッソウ スル
Author/Editor
木村真也著
Publication, Distribution, etc.
Publication Date
2001.11
Publication Date (W3CDTF)
2001
Size
24cm