High-level verification : methods and tools for verification of system-level designs

Author: Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta ; with chapter 6 contributed by Malay K. Ganai and chapter 8 contributed by Zachary Tatlock

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Material Type: 図書
ISBN: 9781441993588
Title: High-level verification : methods and tools for verification of system-level designs
Author/Editor: Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta ; with chapter 6 contributed by Malay K. Ganai and chapter 8 contributed by Zachary Tatlock
Author Heading: Kundu, Sudipta
Gupta, Rajesh Kumar
Lerner, Sorin
Ganai, Malay K.
Tatlock, Zachary
Publication, Distribution, etc.: Springer
Publication Date: c2011
Publication Date (W3CDTF): 2011
Size: 25 cm
Place of Publication (Country Code): us
Text Language Code: en
Subject Heading: Integrated circuits -- Verification
Systems on a chip -- Testing
Systems on a chip -- Design
LCC: TK7874.58
Target Audience: 一般
Note (General): Includes bibliographical references and index
Related Material (URI): https://ci.nii.ac.jp/ncid/BC0453030X#entity
https://lccn.loc.gov/2011928550
Data Provider (Database): 国立情報学研究所 : CiNii Research
Original Data Provider (Database): CiNii Books
https://ci.nii.ac.jp/books
NCID: https://ci.nii.ac.jp/ncid/BC0453030X : BC0453030X
LC Control Number: 2011928550
https://lccn.loc.gov/2011928550